OR3T30
Key Features
- PAL is a trademark of Advanced Micro Devices, Inc. † IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. Table
- ORCA Series 3 (3C and 3T) FPGAs Device OR3T20 OR3T30 OR3C/3T55 OR3C/3T80 OR3T125 System Gates‡ 36K 48K 80K 116K 186K LUTs 1152 1568 2592 3872 6272 Registers 1872 2436 3780 5412 8400 Max User RAM 18K 25K 42K 62K 100K User I/Os 196 228 292 356 452 Array Size 12 x 12 14 x 14 18 x 18 22 x 22 28 x 28 Process Technology 0.3 µm/4 LM 0.3 µm/4 LM 0.3 µm/4 LM 0.3 µm/4 LM 0.3 µm/4 LM ‡ The system gate counts range from a logic-only gate count to a gate count assuming 30% of the PFUs/SLICs being used as RAMs. The logic-only gate count includes each PFU/SLIC (counted as 108 gates per PFU/SLIC), including 12 gates per LUT/FF pair (eight per PFU), and 12 gates per SLIC/FF pair (one per PFU). Each of the four PIOs per PIC is counted as 16 gates (two FFs, fast-capture latch, output logic, CLK drivers, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 32 x 4 RAM (or 512 gates) per PFU. ORCA Series 3C and 3T FPGAs Data Sheet June 1999 Table of Contents Contents Page Contents Page
