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TAAD08JU2 - T1/E1/J1 ATM Processor

Description

11 Pin Definitions 12 Pin Description 12 Package Pin Layout 21 Block Diagram 27 Software Components 28 9.1 Firmware29 9.2 Device Manager29 9.3 Setup File Utility (SFU) 30 9.4 TAAD08JU2 Application Code31 9.5 System Software32 9.6 Software Development Environment 32 9.7 Notes 33 Functional Overview3

Features

  • s s System-on-a-chip integrated circuit supports lowspeed ATM access for next-generation wireless base transmission station (BTS), base station controller (BSC), node-B, radio network controller (RNC), and remote access concentrator (RAC).

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Datasheet Details

Part number TAAD08JU2
Manufacturer Agere Systems
File Size 2.28 MB
Description T1/E1/J1 ATM Processor
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    www.DataSheet4U.com Preliminary Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 1 Features s s System-on-a-chip integrated circuit supports lowspeed ATM access for next-generation wireless base transmission station (BTS), base station controller (BSC), node-B, radio network controller (RNC), and remote access concentrator (RAC) applications. IC provides an integrated octal framer that supports T1/E1/J1 formats. Supports inverse multiplexing for ATM (IMA) over selected group and link mappings ranging from four two-link groups up to one eight-link group per ATM Forum AF-PHY-0086.001. Integrates an ATM adaptation layer 2 (AAL2) segmentation and reassembly (SAR) function for support of low-speed data or voice traffic per ITU I.363.2.
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