TF1004A Datasheet | Agere Systems

Data Sheet August 1999 LG1600FXH Clock and Data Regenerator Features s s s s s s s s s s Integrated clock recovery and data retiming Surface-mount package Single ECL supply Robust FPLL design Operation up to BER = 1e- 3 SONET/SDH patible loss of signal alarm High effective Q allows long run lengths Jitter tolerance exceeding ITU-T/Bellcore Low clock jitter generation: typical <0.005 UI Standard and custom data rates 0.50 Gbits/s- 5.5 Gbits/s plementary 50 Ω I/Os s Figure 1. LG1600FXH Open View Applications s SONET/SDH receiver terminals and regenerators OC-12 through OC-96/STM-4 through STM-32 SONET/SDH test equipment Proprietary bit rate systems Digital video transmission Clock...