Datasheet4U Logo Datasheet4U.com

TLIU04C1 - TLIU04C1 Quad T1/E1 Line Interface

Description

8 Microprocessor Mode 8 Overview 8 Pin Information 9 System Interface Pin Options 14 Microprocessor Configuration Modes 14 Microprocessor Interface Pinout Definitions 15 Microprocessor Clock (MPCLK) Specifications 16 Internal Chip Select Function 16 Microprocessor Interface Register Architecture

Features

  • s s Transmitter includes transmit encoder (B8ZS or HDB3), pulse shaping, and line driver. Five pulse equalization settings for template compliance at DSX cross connect. Receive includes equalization, digital clock and data recovery (immune to false lock), and receive decoder (B8ZS or HDB3). CEPT/E1 interference immunity as required by G.703. Transmit jitter.

📥 Download Datasheet

Datasheet preview – TLIU04C1

Datasheet Details

Part number TLIU04C1
Manufacturer Agere Systems
File Size 1.29 MB
Description TLIU04C1 Quad T1/E1 Line Interface
Datasheet download datasheet TLIU04C1 Datasheet
Additional preview pages of the TLIU04C1 datasheet.

📁 Similar Datasheet

  • TLI493D-A2B6 - Low Power 3D Hall Sensor (Infineon)
  • TLI493D-W2BW - Low power 3D Hall sensor (Infineon)
  • TLI4961-1L - Hall Effect Latch (Infineon)
  • TLI4961-1M - Hall Effect Latch (Infineon)
  • TLI4963-1M - High Precision Automotive Hall Effect Latch (Infineon)
  • TLI4963-2M - High Precision Automotive Hall Effect Latch (Infineon)
  • TLI4965-5M - High Precision Hall Effect Switch (Infineon)
  • TLI4966G - High Precision Hall-Effect Switch (Infineon)
  • TLI4970-D025T4 - Coreless magnetic current sensor (Infineon)
  • TLI4970-D050T4 - High precision miniature coreless magnetic current sensor (Infineon)
Other Datasheets by Agere Systems

    Full PDF Text Transcription

    Click to expand full text
    Advance Data Sheet, Rev. 2 April 1999 TLIU04C1 Quad T1/E1 Line Interface Features s s Transmitter includes transmit encoder (B8ZS or HDB3), pulse shaping, and line driver. Five pulse equalization settings for template compliance at DSX cross connect. Receive includes equalization, digital clock and data recovery (immune to false lock), and receive decoder (B8ZS or HDB3). CEPT/E1 interference immunity as required by G.703. Transmit jitter <0.02 UI. Receive generated jitter <0.05 UI. Jitter attenuator selectable for use in transmit or receive path. Jitter attenuation characteristics are data pattern independent. For use with 100 Ω DS1 twisted-pair, 120 Ω E1 twisted-pair, and 75 Ω E1 coaxial cable. Common part available for transmit/receive transformers.
    Published: |