TTSV02622 - STS-24 Backplane Transceiver

Description

The TTSV02622 can support a 1.24 Gbits/s interface for backplane connections.

The 1.24 Gbits/s interface is implemented as dual 622 Mbits/s LVDS links.

Features

s s s s Low-power 3.3 V supply.
40 °C to +125 °C industrial temperature range. 272-pin ball grid array (PBGA) package. www. DataSheet4U. com Allows wide range of.

Agere Systems

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Datasheet Details

Part number	TTSV02622
Manufacturer	Agere Systems
File Size	1.13 MB
Description	STS-24 Backplane Transceiver
Datasheet	TTSV02622 Datasheet
Additional preview pages of the TTSV02622 datasheet.

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Full PDF Text Transcription

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Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Features s s s s Low-power 3.3 V supply. –40 °C to +125 °C industrial temperature range. 272-pin ball grid array (PBGA) package. www.DataSheet4U.com Allows wide range of applications for SONET network termination application as well as generic data moving for high-speed backplane data transfer. Clock/data recovery (CDR) function for high-speed serial backplane data transfer. CDR function uses Agere Systems Inc. proven 622 Mbits/s serial interface core. Two-channel CDR function provides 622 Mbits/s serial interface per channel for a total chip bandwidth of 1.24 Gbits/s (full duplex). Low-voltage differential signaling (LVDS) I/Os for CDR and reference clock signals. 8:1 data multiplexing/demultiplexing (MUX/ deMUX) for 77.

Published: Nov 4, 2008 |