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A3940 - Full-Bridge Power MOSFET Controller

General Description

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Copyright © 2003 Allegro MicroSystems, Inc.

Measured on “High-K” multi-layer PWB per JEDEC Standard JESD51-7.

Key Features

  • include supply under/overvoltage, thermal shutdown, and motor lead short-to-battery and short-to-ground fault notification, and a programmable dead-time adjustment for cross-conduction prevention. The overvoltage trip point is user adjustable. The A3940 is supplied in a choice of two power packages, a 28-pin TSSOP with an exposed thermal pad (package type LP), and a 28-pin wide-body SOIC (package type LW). Both package types are available in lead (Pb) free versions, with 100 % matte-tin leadframe.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Data Sheet 29319.100J 3940 A3940KLP (TSSOP with exposed thermal pad) A3940KLW (SOIC) Approx. 2X actual size. ABSOLUTE MAXIMUM RATINGS Load Supply Voltage Range, VBB, VDRAIN, CP1 ........................ -0.6 V to +40 V Output Voltage Ranges, LSS .............................. -2 V to +6.5 V GHA/GHB, VGHX ......... -2 V to +55 V SA/SB, VSX .................. -2 V to +45 V GLA/GLB, VGLX .......... -2 V to +16 V CA/CB, VCX .............. -0.6 V to +55 V CP2,VCP, VIN ........... -0.6 V to +52 V Logic Input/Output Voltage Range VIN, VOUT .................... -0.3 V to +6.5 V Operating Temperature Range, TA ............................ -40°C to +135°C Junction Temperature, TJ .......... +150°C* Storage Temperature Range, TS ............................