AS7C31024B Description
The AS7C31024B is a high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 131,072 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns are ideal for high performance applications.
AS7C31024B Key Features
- Industrial and mercial temperatures
- Organization: 131,072 words x 8 bits
- High speed
- 10/12/15/20 ns address access time
- 5, 6, 7, 8 ns output enable access time
- Low power consumption: ACTIVE
- 252 mW / max @ 10 ns
- Easy memory expansion with CE1, CE2, OE inputs
- TTL/LVTTL-patible, three-state I/O
- 32-pin JEDEC standard packages