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AS7C34096A - 3.3V 512K x 8 CMOS SRAM

Description

The AS7C34096A is a high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as 524,288 words × 8 bits.

It is designed for memory applications where fast data access, low power, and simple interfacing are desired.

Features

  • - 10/12/15/20 ns address access time - 4/5/6/7 ns output enable access time - 650 mW / max @ 10 ns - 18 mW / max CMOS U 4 t . c om AS7C34096A ® 3.3V 512K × 8 CMOS SRAM.
  • Equal access and cycle times.
  • Easy memory expansion with CE, OE inputs.
  • TTL-compatible, three-state I/O.
  • JEDEC standard packages - 400 mil 36-pin SOJ - 44-pin TSOP 2 - 48 pin BGA. 6 X 9mm Pin arrangements A0 A1 A2 A3 A4 CE I/O1 I/O2 VCC GND I/O3 I/O4 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10.

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Datasheet preview – AS7C34096A

Datasheet Details

Part number AS7C34096A
Manufacturer Alliance Semiconductor Corporation
File Size 119.81 KB
Description 3.3V 512K x 8 CMOS SRAM
Datasheet download datasheet AS7C34096A Datasheet
Additional preview pages of the AS7C34096A datasheet.

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  • AS7C33128FT32B - (AS7C33128FT32B / AS7C33128FT36B) 3.3V 128K x 32/36 Flow Through Synchronous SRAM
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Full PDF Text Transcription

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February 2004 e e hAS7C34096 • Pin compatible to S • Industrial and commercial temperature a 524,288 words × 8 bits t • Organization: a and ground pins • Center power D .speed • High w w w• Low power consumption: ACTIVE Features - 10/12/15/20 ns address access time - 4/5/6/7 ns output enable access time - 650 mW / max @ 10 ns - 18 mW / max CMOS U 4 t .c om AS7C34096A ® 3.3V 512K × 8 CMOS SRAM • Equal access and cycle times • Easy memory expansion with CE, OE inputs • TTL-compatible, three-state I/O • JEDEC standard packages - 400 mil 36-pin SOJ - 44-pin TSOP 2 - 48 pin BGA.
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