ASM3P2531A Datasheet | Alliance Semiconductor Corporation

Features FCC approved method of EMI attenuation. Generates a low EMI spread spectrum of the input clock frequency. Optimized for input frequency range between 35MHz - 55MHz. Internal loop filter minimizes external ponents and board space. Frequency Deviation: ±1.65%. Low inherent cycle-to-cycle jitter. 3.3 V or 5 V operating voltage. CMOS/TTL patible inputs and outputs. Ultra low power CMOS design: 5.50 m A @3.3 V. Supports notebook VGA and other LCD timing controller applications. Available in 8-pin SOIC and TSSOP. dependent signals. It allows significant system cost savings by reducing the number of circuit board layers and shielding traditionally required to pass EMI regulations. The ASM3P2531A modulates the output of a single PLL in order to spread the bandwidth of a synthesized clock, thereby decreasing the peak amplitudes of its harmonics. This results in significantly lower system EMI pared to the typical narrow band signal produced by oscillators and most clock generators. Lowering EMI by increasing a signal’s bandwidth is called spread spectrum clock generation. The ASM3P2531A uses the most efficient and optimized modulation profile approved by the FCC and is implemented by using a proprietary all-digital method. Product Description The ASM3P2531A is a versatile spread spectrum frequency modulator designed specifically for a wide range of clock frequencies. It reduces electromagnetic interference (EMI) at the clock source allowing systemwide reduction of EMI of downstream clock and data Applications The ASM3P2531A is targeted toward the notebook VGA chip and other displays using an LVDS interface, PC peripheral devices, and embedded systems Block Diagram STOP VDD Modulation CLKIN Crystal Oscillator Frequency Divider Feedback Divider Phase Detector Loop Filter Output Divider MODOUT Low Frequency EMI Reduction Notice: The information in this document is subject to change without notice. 1 of 8 November 2003 rev...