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AS4C128M32MD4-062BAN Datasheet 2Gb/4Gb/8Gb LPDDR4

Manufacturer: Alliance Semiconductor

Overview: 2Gb/4Gb/8Gb LPDDR4 Revision History For 2Gb/4Gb/8Gb LPDDR4 200ball FBGA Package Revision Rev 1.0 Rev 1.1 Details Initial Release Updates in Table.1, Table.27, 28 & MR1 notes Date Aug 2020 Mar 2021 Confidential - 1 of 64 - Rev. 1.1 Mar. 2020 2Gb/4Gb/8Gb LPDDR4 1 Overview The LPDDR4 SDRAM is organized as 1 or 2 channels per device, and individual channel is 8-banks and 16-bits. This product uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 16n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 16n bits prefetched to achieve very high bandwidth. 1.

Download the AS4C128M32MD4-062BAN datasheet PDF. This datasheet also includes the AS4C128M16MD4-062BAN variant, as both parts are published together in a single manufacturer document.

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Key Features

  • The 2Gb/4Gb/8Gb LPDDR4 SDRAM offers the following key features:.
  • Configuration: - x32 for 2-channels per device (AS4C64M32MD4 , AS4C128M32MD4, AS4C256M32MD4) - x16 for 1-channel per device (AS4C128M16MD4, AS4C256M16MD4) - 8 internal banks per each channel.
  • On-Chip ECC: - Single-bit error correction (per 64-bits), which will maximize reliability - Optional ERR output signal per channel, which indicates ECC event occurrence - ECC Register, which controls ECC function.
  • Low-voltage C.

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