AS4C128M32MD4-062BAN Description
This product uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 16n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock.
AS4C128M32MD4-062BAN Key Features
- Configuration
- x32 for 2-channels per device (AS4C64M32MD4 , AS4C128M32MD4, AS4C256M32MD4)
- x16 for 1-channel per device (AS4C128M16MD4, AS4C256M16MD4)
- 8 internal banks per each channel
- On-Chip ECC
- Single-bit error correction (per 64-bits), which will maximize reliability
- Optional ERR output signal per channel, which indicates ECC event occurrence
- ECC Register, which controls ECC function
- Low-voltage Core and I/O Power Supplies
- VDD2 /VDDQ = 1.06-1.17V, VDD1 = 1.70-1.95V