Datasheet4U Logo Datasheet4U.com

AS4C256M16MD4-062BAN - 2Gb/4Gb/8Gb LPDDR4

This page provides the datasheet information for the AS4C256M16MD4-062BAN, a member of the AS4C128M16MD4-062BAN 2Gb/4Gb/8Gb LPDDR4 family.

Features

  • The 2Gb/4Gb/8Gb LPDDR4 SDRAM offers the following key features:.
  • Configuration: - x32 for 2-channels per device (AS4C64M32MD4 , AS4C128M32MD4, AS4C256M32MD4) - x16 for 1-channel per device (AS4C128M16MD4, AS4C256M16MD4) - 8 internal banks per each channel.
  • On-Chip ECC: - Single-bit error correction (per 64-bits), which will maximize reliability - Optional ERR output signal per channel, which indicates ECC event occurrence - ECC Register, which controls ECC function.
  • Low-voltage C.

📥 Download Datasheet

Datasheet preview – AS4C256M16MD4-062BAN

Datasheet Details

Part number AS4C256M16MD4-062BAN
Manufacturer Alliance Semiconductor
File Size 1.24 MB
Description 2Gb/4Gb/8Gb LPDDR4
Datasheet download datasheet AS4C256M16MD4-062BAN Datasheet
Additional preview pages of the AS4C256M16MD4-062BAN datasheet.

📁 Similar Datasheet

  • AS4C1024 - 1M x 1 DRAM (Austin Semiconductor)
  • AS4C1259 - 256K x 1 DRAM (Austin Semiconductor)
  • AS4C1259883C - 256K x 1 DRAM (Austin Semiconductor)
  • AS4C1M16S - 1M x 16 bit Synchronous DRAM (Alliance Memory)
  • AS4C1M16S-C - 1M x 16 bit Synchronous DRAM (Alliance Memory)
  • AS4C1M16S-I - 1M x 16 bit Synchronous DRAM (Alliance Memory)
  • AS4C4067 - 64K x 4 DRAM (Austin Semiconductor)
  • AS4C4256 - (Austin Semiconductor)
  • AS4C4256883C - 256K x 4 DRAM (Austin Semiconductor)
  • AS4C4M4 - 16M FPM DRAM (Austin Semiconductor)
Other Datasheets by Alliance Semiconductor

Full PDF Text Transcription

Click to expand full text
2Gb/4Gb/8Gb LPDDR4 Revision History For 2Gb/4Gb/8Gb LPDDR4 200ball FBGA Package Revision Rev 1.0 Rev 1.1 Details Initial Release Updates in Table.1, Table.27, 28 & MR1 notes Date Aug 2020 Mar 2021 Confidential - 1 of 64 - Rev. 1.1 Mar. 2020 2Gb/4Gb/8Gb LPDDR4 1 Overview The LPDDR4 SDRAM is organized as 1 or 2 channels per device, and individual channel is 8-banks and 16-bits. This product uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 16n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock.
Published: |