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AS4C256M16MD4V-062BAN - 4Gbit LPDDR4X SDRAM

This page provides the datasheet information for the AS4C256M16MD4V-062BAN, a member of the AS4C128M16MD4V-062BAN 4Gbit LPDDR4X SDRAM family.

Features

  • The 2Gbit /4Gbit/8Gbit LPDDR4X SDRAM offers the following key features:.
  • Configuration: - x32 for 2-channels per device (AS4C256M32MD4V) - x16 for 1-channel per device (AS4C128M16MD4V/AS4C256M16MD4V) - 8 internal banks per each channel.
  • On-Chip ECC: - Single-bit error correction (per 64-bits), which will maximize reliability - Optional ERR output signal per channel, which indicates ECC event occurrence - ECC Register, which controls ECC function.
  • Low-voltage Core and I/O Power Su.

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Datasheet preview – AS4C256M16MD4V-062BAN

Datasheet Details

Part number AS4C256M16MD4V-062BAN
Manufacturer Alliance Semiconductor
File Size 2.91 MB
Description 4Gbit LPDDR4X SDRAM
Datasheet download datasheet AS4C256M16MD4V-062BAN Datasheet
Additional preview pages of the AS4C256M16MD4V-062BAN datasheet.

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Full PDF Text Transcription

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Revision History For 2Gbit /4Gbit/8Gbit LPDDR4X SDRAM 200ball FBGA Package Revision Rev 1.0 Rev 1.1 Details Initial Release Add 2Gb,4Gb LPDDR4X Date Mar 2021 Apr 2023 Confidential -1/65- Rev. 1.1 Apr. 2023 1 Overview The Alliance LPDDR4X SDRAM is organized as 1 or 2 channels per device, and individual channel is 8-banks and 16-bits. This product uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 16n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 16n bits prefetched to achieve very high bandwidth. 1.
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