AS4C256M32MD4V-062BAN Datasheet | Alliance Semiconductor

Overview The Alliance LPDDR4X SDRAM is organized as 1 or 2 channels per device, and individual channel is 8-banks and 16-bits. This product uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 16n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 16n bits prefetched to achieve very high bandwidth. 1.1 Features The 2Gbit /4Gbit/8Gbit LPDDR4X SDRAM offers the following key features : - Configuration: - x32 for 2-channels per device (AS4C256M32MD4V) - x16 for 1-channel per device (AS4C128M16MD4V/AS4C256M16MD4V) - 8 internal banks per each channel - On-Chip ECC: - Single-bit error correction (per 64-bits), which will maximize reliability - Optional ERR output signal per channel, which indicates ECC event occurrence...