AS6UA51216 Datasheet | Alliance Semiconductor

Features - - - - - - - - AS6UA51216 Intelliwatt™ active power circuitry Industrial and mercial temperature ranges available Organization: 524,288 words × 16 bits 2.7V to 3.6V at 55 ns 2.3V to 2.7V at 70 ns 1.65V to 2.3V at 100 ns Low power consumption: ACTIVE - 144 m W at 3.6V and 55 ns - 68 m W at 2.7V and 70 ns - 28 m W at 2.3 V and 100 ns - Low power consumption: STANDBY - 72 µW max at 3.6V - 41 µW max at 2.7V - 28 µW max at 2.3V - 1.2V data retention - Equal access and cycle times - Easy memory expansion with CS, OE inputs - Smallest footprint packages - 48-ball FBGA - 400-mil 44-pin TSOP II - ESD protection ≥ 2000 volts - Latch-up current ≥ 200 m A Logic block diagram A0 A1 A2 A3 A4 A6 A7 A8 A12 A13 I/O1- I/O8 I/O9- I/O16 WE Row Decoder VDD 512K × 16 Array (8,388,608) VSS Pin arrangement (top view) 44-pin 400-mil TSOP II A4 1 A5 44 A3 2 43 A6 A2 3 42 A7 A1 4 41 OE 5 A0 UB 40 LB 6 39 CS I/O16 I/O1 7 38 I/O15 I/O2 8 37 I/O14 I/O3 9 36 I/O13 I/O4 10 35 VCC VSS 11 34 VSS VCC 12 33 I/O5 13 32 I/O12 I/O6 I/O11 14 31 I/O7 I/O10 15 30 I/O8 I/O9 16 29 WE A8 17 28 A18 18 A9 27 A17 A10 19 26 A16 20 25 A11 A15 21 A12 24 A14 22 A13 23 Note: A “MODE” pad is to be placed between pins 33 and 34 and 11 and 12, shorted. The bonding of this pad to VCC or VSS configures the device. There should only be 44+2+2 pads on the chip. Two extra VCC to separate out Array from Peripheral and Two-Mode Pads. I/O buffer Control circuit Column decoder A5 A9 A10 A11 A14 A15 A16 A17 A18 UB OE LB CS 48-CSP Ball-Grid-Array Package A B C D E F G H 1 LB I/O9 I/O10 VSS VCC I/O15 I/O16 A18 2 3 OE A0 A3 UB I/O11 A5 I/O12 A17 I/O13 VSS I/O14 A14 NC A12 A8 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CS I/O2 I/O4 I/O5 I/O6 WE A11 6 NC I/O1 I/O3 VCC VSS I/O7 I/O8 NC Selection guide VCC Range Product AS6UA51216 AS6UA51216 AS6UA51216 Min (V) 2.7 2.3 1.65 Typ2 (V) 3.0 2.5 2.0 Max (V) 3.6 2.7 2.3 Speed (ns) 55 70 100 Power Dissipation Operating (ICC1) Max (m A) 2 1 1 Standby (ISB2) Max (µA) 20 15...