Datasheet Details
| Part number | AS7C164 |
|---|---|
| Manufacturer | Alliance Semiconductor |
| File Size | 187.10 KB |
| Description | 5V 8K X 8 CMOS SRAM |
| Datasheet |
 AS7C164 Datasheet
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Key Features
- e Low and CE2 is High for read cycle. Address valid prior to or coincident with CE1 transition Low and CE2 transition High. All read cycle timings are referenced from the last valid address to the first transitioning address. CE1 or WE must be High or CE2 Low during address transitions. Either CE or WE asserting high terminates a write cycle. All write cycle timings are referenced from the last valid address to the first transitioning address. CE1 and CE2 have identical timing. 2V data retention.