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AS7C256L - 32K x 8 CMOS SRAM

Key Features

  • Organization: 32,768 words × 8 bits.
  • High speed.
  • 10/12/15/20/25/35 ns address access time.
  • 3/3/4/5/6/8 ns output enable access time.
  • Low power consumption.
  • Active: 660 mW max (10 ns cycle).
  • Standby: 11 mW max, CMOS I/O 2.75 mW max, CMOS I/O, L version.
  • Very low DC component in active power.
  • 2.0V data retention (L version).
  • Equal access and cycle times.
  • Easy memory expansion with CE and OE inputs.

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Datasheet Details

Part number AS7C256L
Manufacturer Alliance Semiconductor
File Size 124.73 KB
Description 32K x 8 CMOS SRAM
Datasheet download datasheet AS7C256L Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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High Performance 32K×8 CMOS SRAM 32K×8 CMOS SRAM (Common I/O) AS7C256 AS7C256L FEATURES • Organization: 32,768 words × 8 bits • High speed – 10/12/15/20/25/35 ns address access time – 3/3/4/5/6/8 ns output enable access time • Low power consumption – Active: 660 mW max (10 ns cycle) – Standby: 11 mW max, CMOS I/O 2.75 mW max, CMOS I/O, L version – Very low DC component in active power • 2.0V data retention (L version) • Equal access and cycle times • Easy memory expansion with CE and OE inputs • TTL-compatible, three-state I/O • 28-pin JEDEC standard packages – 300 mil PDIP and SOJ Socket compatible with 7C512 and 7C1024 – 330 mil SOIC – 8×13.