Datasheet Summary
December 2002
AS7C33128NTD32A AS7C33128NTD36A
- 9 .î 65$0 ZLWK 17'TM
Features
- Organization: 131,072 words × 32 or 36 bits NTD™1 architecture for efficient bus operation
- Fast clock speeds to 166 MHz in LVTTL/LVCMOS
- Fast clock to data access: 3.5/4.0/5.0 ns
- Fast OE access time: 3.5/4.0/5.0 ns
- Fully synchronous operation
- Flow-through or pipelined mode
- Asynchronous output enable control
1. NTD™ is a trademark of Alliance Semiconductor Corporation.
Logic block diagram
- Economical 100-pin TQFP package
- Byte write enables
- Clock enable for operation hold
- Multiple chip enables for easy expansion
- 3.3V core power supply
- 2.5V or 3.3V I/O operation with separate...
