Alliance Semiconductor AS7C513B
The AS7C513B is a high performance CMOS 524,288-bit Static Random Access Memory (SRAM) device organized as 32,768 words × 16 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired. The chip enable input CE permits easy memory expansion with multiple-bank memory systems.| Part No. | AS7C513B |
|---|---|
| Datasheet | AS7C513B Download |
| Manufacturer |  Alliance Semiconductor |
| Description | 5V 32K x 16 CMOS SRAM |
| Buy | Stock & Price |
FEATURES
● Industrial and commercial temperature● Organization: 32,768 words × 16 bits
● Center power and ground pins
● High speed
● 10/12/15/20 ns address access time
● 5, 6, 7, 8 ns output enable access time
● Low power consumption: ACTIVE
● 605mW / max @ 10 ns
● Low power consumption: STANDBY
● 55 mW / max CMOS I/O
● 6T 0.18u CMOS Technology
● Easy memory expansion with CE, OE inputs
● TTL-compatible, three-state I/O
● 44-pin JEDEC standard package
● 400 mil SOJ
● 400 mil TSOP 2
● ESD protection > 2000 volts
● Latch-up current > 200 mA Row decoder A8 A9 A10 A11 A12 A13 A14 AS7C513B Logic block diagram A0 A1 VCC A2 32K × 16 GND A3 Array A4 A5 A6 A7 I/O0–I/O7 I/O8–I/O15 I/O buffer Control circuit WE Column decoder UB OE LB CE Pin arrangement 44-Pin SOJ, TSOP 2 (400 mil) NC 1 A3 2 A2 3 A1 4 A0 5 CE 6 I/O0 7 I/O1 8 I/O2 9 I/O3 10 VCC 11 GND 12 I/O4 13 I/O5 14 I/O6 15 I/O7 16 WE 17 A14 18 A13 19 A12 20 A11 21 NC 22 44 A4 43 A5 42 A6 41 OE 40 UB 39 LB 38 I/O15 37 I/O14 36 I/O13 35 I/O12...
