D1s
D1s is The Most Cost-Effective Decoding Platform Processor manufactured by Allwinner.
Features
- RISC CPU
- Memories
- Embedded with 64 MB DDR2, clock frequency up to 533 MHz
- Three SD/MMC host controller (SMHC) interfaces: SD3.0/SDIO3.0/e MMC5.0
- Video Engine
- H.265/H.264/MPEG-1/MPEG-2/MPEG-4/JPEG/VC1/Xvid/Sorenson Spark decoding, up to 1080p@60fps
- JPEG/MJPEG encoding, up to 1080p@60fps
- Video and Graphics
- Allwinner Smart Color2.0 post processing for an excellent display experience
- Supports de-interlacer (DI) up to 1080p@60fps
- Supports Graphic 2D (G2D) hardware accelerator including rotate, mixer, LBC depression functions
- Video Output
- RGB interface up to 1920 x 1080@60fps
- Dual link LVDS interface up to 1920 x 1080@60fps
- 4-lane MIPI DSI up to 1920 x 1200@60fps
- CVBS OUT interface, supporting NTSC and PAL format
- Video Input
- 8-bit digital camera interface
- CVBS IN interface, supporting NTSC and PAL format
- Analog Audio Codec
- 2 DACs and 3 ADCs
- Analog audio interfaces: HPOUTL/R, MICIN3P/N, LINEINL/R, FMINL/R
- Two I2S/PCM external interfaces (I2S1, I2S2)
- Maximum 8 digital PDM microphones (DMIC)
- OWA TX and OWA RX, pliance with S/PDIF interface
- Security System
- AES, DES, 3DES, RSA, MD5, SHA, HMAC
- Integrated 2 Kbits OTP storage space
- External Peripherals
- USB 2.0 DRD (USB0) and USB 2.0 HOST (USB1)
- 10/100/1000 Mbps Ethernet port with RGMII and RMII interfaces
- Up to 6 UART controllers (UART0, UART1, UART2, UART3, UART4, UART5)
- Up to 2 SPI controllers (SPI0, SPI1)
- Up to 4 TWI controllers (TWI0, TWI1, TWI2, TWI3)
- CIR RX and CIR TX
- 8 independent PWM channels (PWM0 to PWM7)
- 1-ch GPADC
- 4-ch TPADC
-...
