F1C600
Key Features
- 2. Features 2.1. CPU Architecture The F1C600 platform is based on ARM9 CPU architecture
- Five-stage pipeline architecture
- Support 16KByte D-Cache
- Support 32KByte I-Cache 2.2. Memory Subsystem This section consists of internal memory and external memory
- SD/MMC Interface Boot ROM
- Internal memory
- On-Chip ROM boot loader
- Support system boot from SPI Nor/Nand Flash, and SD/TF card
- Support system code download through USB OTG SDRAM
- SIP DDR1 SD/MMC Interface
Applications
- Video Playback
