7032STC Datasheet | Altera Corporation

Features ... - - - .. - - - - High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX® architecture 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices - ISP circuitry patible with IEEE Std. 1532 Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells plete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2) 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect) PCI-pliant devices available f For information on in-system programmable 3.3-V MAX 7000A or 2.5-V MAX 7000B devices, see the MAX 7000A Programmable Logic Device Family Data Sheet or the MAX 7000B Programmable Logic Device Family Data Sheet. Table 1. MAX 7000 Device Features Feature Usable gates Macrocells Logic array blocks Maximum user I/O pins t PD (ns) t SU (ns) t FSU (ns) t CO1 (ns) f CNT (MHz) EPM7032 600 32 2 36 6 5 2.5 4 151.5 EPM7064 1,250 64 4 68 6 5 2.5 4 151.5 EPM7096 1,800 96 6 76 7.5 6 3 4.5 125.0 EPM7128E 2,500 128 8 100 7.5 6 3 4.5 125.0 EPM7160E 3,200 160 10 104 10 7 3 5 100.0 EPM7192E 3,750 192 12 124 12 7 3 6 90.9 EPM7256E 5,000 256 16 164 12 7 3 6 90.9 Altera Corporation DS-MAX7000-6.7 MAX 7000 Programmable Logic Device Family Data Sheet Table 2. MAX 7000S Device Features Feature Usable gates Macrocells Logic array blocks Maximum user I/O pins t PD (ns) t SU (ns) t FSU (ns) t CO1 (ns) .. f CNT (MHz) EPM7032S 600 32 2 36 5 2.9 2.5 3.2 175.4 - - - - - EPM7064S 1,250 64 4 68 5 2.9 2.5 3.2...