A16450 Datasheet | Altera Corporation

® Universal Asynchronous Receiver/Transmitter Data Sheet September 1996, ver. 1 Features s s s s s s s s s a16450 Mega Core function implementing a universal asynchronous receiver/transmitter (UART) Optimized for FLEX® and MAX® architectures Programmable word length, stop bits, and parity Full duplex operation Programmable baud rate generator Prioritized interrupt control Internal diagnostic/loopback capabilities Uses approximately 372 FLEX logic elements (LEs) Functionally based on the National Semiconductor Corporation NS16450 device, except as noted in “Variations & Clarifications” on page 79 General Description The a16450 Mega Core function implements a universal asynchronous receiver/transmitter (UART), which provides an interface between a microprocessor and a serial munications channel. The a16450 .. receives and transmits data in a variety of configurations, including 5-, 6-, 7-, or 8-bit data words; odd, even, or no parity; and 1, 1.5, or 2 stop bits. The a16450 includes an internal baud rate generator and interrupt control. See Figure 1. Figure 1. a16450 Symbol A16450 n ADS CLK CS0 CS1 n CS2 n BAUDOUT n CTS CSOUT n DCD DDIS n DSR n DTR MR INTR RCLK n OUT1 RD n OUT2 n RD n RTS n RI SOUT SIN DOUT[7..0] WR n WR A[2..0] DIN[7..0] Altera Corporation A-DS-A16450-01 65 a16450 Universal Asynchronous Receiver/Transmitter Data Sheet Table 1 describes the input and output ports of the a16450. Table 1. a16450 Ports (Part 1 of 2) Name nads Type Input Polarity Low Description Address strobe. Enable signal to the address input receiver. The positive edge of nads latches the register address bus into the address input register. Clock. Provides the master timing reference to the a16450. Chip select 0. The a16450 is selected when cs0, cs1, and ncs2 are asserted, which permits read and write transactions to internal registers. Chip select 1. The a16450 is selected when cs0, cs1, and ncs2 are asserted, which permits read and write transactions to...