A6402 Datasheet | Altera Corporation

Features s s s s s s s a6402 Mega Core function implementing a universal asynchronous receiver/transmitter (UART) Optimized for FLEX® and MAX® architectures Uses approximately 162 FLEX logic elements (LEs) Programmable word length, stop bits, and parity Full duplex operation Includes status flags for parity, framing, and overrun errors Functionally based on the Harris HD-6402 device, except as noted in the “Variations & Clarifications” section on page 63 General Description The a6402 Mega Core function implements a universal asynchronous receiver/transmitter (UART), which provides an interface between a microprocessor and a serial munications channel. See Figure 1. Figure 1. a6402 Symbol A6402 cls1 cls2 crl ndrr epe mr pi rrc rri sbs ntbrl tbr[7..0] trc dr fe oe pe rbr[7..0] tbre tre tro Altera Corporation A-DS-A6402-01 57 a6402 Universal Asynchronous Receiver/Transmitter Data Sheet Ports Table 1 shows the input and output ports for the a6402. Table 1. a6402 Ports Name cls1 cls2 Type Input Polarity - Description Character length select bits. These bits determine the length of the data word. 00 = 5-bit word format 01 = 6-bit word format 10 = 7-bit word format 11 = 8-bit word format Control register load. Controls how the data word is loaded into the control register. Data received reset. Clears the dr output. Even parity enable. When high, even parity; when low, odd parity. Master reset. Clears the pe, fe, dr, and oe outputs, and asserts the tre and tbre outputs. Parity inhibit. When pi is asserted, parity is neither generated nor checked. Receiver register clock. Operates at 16 times the receive data rate. Receiver register input. Serial input data. Stop bit select. When high, sbs generates 2 stop bits (1.5 stop bits for 5-bit format); when low, sbs generates 1 stop bit. Transmitter buffer register load. Enables load of the transmitter buffer register. Transmitter buffer register input bus. Transmitter register clock. Operates at 16 times the transmit...