Click to expand full text
EPF10K100B
®
Embedded Programmable Logic Device
Errata Sheet
July 1998, ver. 1
Preliminary Information
This errata sheet provides updated information for Revision A and Revision B EPF10K100B devices. The die revision is indicated by the third digit of the nine-digit code on the top side of the device. Revision C and higher EPF10K100B devices do not exhibit the conditions described in this document. Under certain voltage conditions, the output buffer delay for Revision A and Revision B EPF10K100B devices is slower than the reported value for I/O pins with the Slow Slew Rate option turned on in the MAX+PLUS® II software. The MAX+PLUS II version 9.0 Timing Analyzer and Simulator report an added output delay of 4.5 ns when the Slow Slew Rate option is turned on.