EPM9560A
Key Features
- High-performance CMOS EEPROM-based programmable logic devices (PLDs) built on third-generation Multiple Array MatriX (MAX®) architecture 5.0-V in-system programmability (ISP) through built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990 High-density erasable programmable logic device (EPLD) family ranging from 6,000 to 12,000 usable gates (see Table 1) 10-ns pin-to-pin logic delays with counter frequencies of up to 144 MHz Fully compliant with the peripheral component interconnect Special Interest Group’s (PCI SIG) PCI Local Bus Specification, Revision 2.2 Dual-output macrocell for independent use of combinatorial and registered logic FastTrack® Interconnect for fast, predictable interconnect delays Input/output registers with clear and clock enable on all I/O pins Programmable output slew-rate control to reduce switching noise MultiVolt™ I/O interface operation, allowing devices to interface with 3.3-V and 5.0-V devices Configurable expander product-term distribution allowing up to 32 product terms per macrocell Programmable power-saving mode for more than 50% power reduction in each macrocell Table
- MAX 9000 Device Features Feature Usable gates Flipflops Macrocells m o .c U 4 t e e h S a at .D w w w
