MAX7000A Datasheet | Altera Corporation

September 2003, ver. 4.5 Includes ® MAX 7000AE MAX 7000A Programmable Logic Device Data Sheet Features ... f - High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array Matri X (MAX®) architecture (see Table 1) - 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability - MAX 7000AE device in-system programmability (ISP) circuitry pliant with IEEE Std. 1532 - EPM7128A and EPM7256A device ISP circuitry patible with IEEE Std. 1532 - Built-in boundary-scan test (BST) circuitry pliant with IEEE Std. 1149.1 - Supports JEDEC Jam Standard Test and Programming Language (STAPL) JESD-71 - Enhanced ISP Features - Enhanced ISP algorithm for faster programming (excluding EPM7128A and EPM7256A devices) - ISP_Done bit to ensure plete programming (excluding EPM7128A and EPM7256A devices) - Pull-up resistor on I/O pins during in-system programming - Pin-patible with the popular 5.0-V MAX 7000S devices - High-density PLDs ranging from 600 to 10,000 usable gates - Extended temperature range For information on in-system programmable 5.0-V MAX 7000 or 2.5-V MAX 7000B devices, see the MAX 7000 Programmable Logic Device Family Data Sheet or the MAX 7000B Programmable Logic Device Family Data Sheet. Altera Corporation DS-M7000A-4.5 MAX 7000A Programmable Logic Device Data Sheet Table 1. MAX 7000A Device Features Feature Usable gates Macrocells Logic array blocks Maximum user I/O pins t PD (ns) t SU (ns) t FSU (ns) t CO1 (ns) f CNT (MHz) EPM7032AE 600 32 2 36 4.5 2.9 2.5 3.0...