EP1K100 Datasheet | Altera

eatures... - Programmable logic devices (PLDs), providing low cost system-on-a-programmable-chip (SOPC) integration in a single device - Enhanced embedded array for implementing megafunctions such as efficient memory and specialized logic functions - Dual-port capability with up to 16-bit width per embedded array block (EAB) - Logic array for general logic functions - High density - 10,000 to 100,000 typical gates (see Table 1) - Up to 49,152 RAM bits (4,096 bits per EAB, all of which can be used without reducing logic capacity) - Cost-efficient programmable architecture for high-volume applications - Cost-optimized process - Low cost solution for high-performance munications applications - System-level Features - Multi Volt TM I/O pins can drive or be driven by 2.5-V, 3.3-V, or 5.0-V devices - Low power consumption - Bidirectional I/O performance (setup time [t SU] and clock-tooutput delay [t CO]) up to 250 MHz - Fully pliant with the peripheral ponent interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 33 MHz or 66 MHz - Extended temperature range Table 1. ACEXTM 1K Device Features Feature Typical gates Maximum system gates Logic elements (LEs) EABs Total RAM bits Maximum user I/O pins EP1K10 10,000 56,000 576 3 12,288 136 EP1K30 30,000 119,000 1,728 6 24,576 171 EP1K50 50,000...