EP1K50 Description
3.4 ACEX 1K Programmable Logic Device Family ® Data Sheet.
EP1K50 Key Features
- Programmable logic devices (PLDs), providing low cost system-on-a-programmable-chip (SOPC) integration in a single devic
- Enhanced embedded array for implementing megafunctions such as efficient memory and specialized logic functions
- Dual-port capability with up to 16-bit width per embedded array block (EAB)
- Logic array for general logic functions
- High density
- 10,000 to 100,000 typical gates (see Table 1)
- Up to 49,152 RAM bits (4,096 bits per EAB, all of which can be used without reducing logic capacity)
- Cost-efficient programmable architecture for high-volume