Altera EP1S25
The table below shows the revision history for Chapter 1 through Chapter 5.| Part No. | EP1S25 |
|---|---|
| Datasheet | EP1S25 Download |
| Manufacturer |  Altera |
| Description | Stratix Device |
| Buy | Stock & Price |
FEATURES
” on page 1–2. Global change from SignalTap to SignalTap II. The DSP blocks in “FEATURES
” on page 1–2 provide dedicated implementation of multipliers that are now “faster than 300 MHz.” Updated -5 speed grade device information in Table 1-6. Add -8 speed grade device information. Format changes throughout chapter. m o c . u 4 t e e h s a t a .d w w w January 2004, v2.2 October 2003, v2.1 July 2003, v2.0●
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● Altera Corporation Section I–1 Preliminary Chapter 5. Reference & Ordering Information Stratix Device Family Data Sheet Stratix Device Handbook, Volume 1 Chapter 2 Date/Version September 2004, v3.1
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● Changes Made Updated fast regional clock networks description on page 2–71. Deleted the word preliminary from the “specification for the maximum time to relock is 100 µs” on page 2–88. Added information about differential SSTL and HSTL outputs in “External Clock Outputs” on page 2–90. Updated notes in Figure 2–55 on page 2–91. Added information about m counter to “Clock Multiplication & Division” on page 2–99.
