Datasheet Details
| Part number | EP1S80B956 |
|---|---|
| Manufacturer | Altera |
| File Size | 3.36 MB |
| Description | (EP1S10 - EP1S80) Stratix Device |
| Datasheet | EP1S80B956_Altera.pdf |
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Overview: Section I. Stratix Device Family Data Sheet This section provides designers with the data sheet specifications for Stratix devices. They contain feature definitions of the internal architecture, configuration and JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, a reference to power consumption, and ordering information for Stratix devices. This section contains the following chapters: ■ ■ ■ ■ ■ Chapter 1. Introduction Chapter 2. Stratix Architecture Chapter 3. Configuration & Testing Chapter 4. DC & Switching Characteristics Revision History Chapter 1 The table below shows the revision history for Chapter 1 through Chapter 5. Date/Version September 2004, v3.1 April 2004, v3.0 ● ● ● ● ● Changes Made Updated Table 1–6 on page 1–5. Main section page numbers changed on first page. Changed PCI-X to PCI-X 1.
| Part number | EP1S80B956 |
|---|---|
| Manufacturer | Altera |
| File Size | 3.36 MB |
| Description | (EP1S10 - EP1S80) Stratix Device |
| Datasheet | EP1S80B956_Altera.pdf |
|
|
|
on page 2–71.
Deleted the word preliminary from the “specification for the maximum time to relock is 100 µs” on page 2–88.
Added information about differential SSTL and HSTL outputs in “External Clock Outputs” on page 2–90.
| Part Number | Description |
|---|---|
| EP1S80 | (EP1S10 - EP1S80) Stratix Device |
| EP1S10 | (EP1S10 - EP1S80) Stratix Device |
| EP1S20 | (EP1S10 - EP1S80) Stratix Device |
| EP1S25 | (EP1S10 - EP1S80) Stratix Device |
| EP1S30 | (EP1S10 - EP1S80) Stratix Device |
| EP1S40 | (EP1S10 - EP1S80) Stratix Device |
| EP1S60 | (EP1S10 - EP1S80) Stratix Device |
| EP1800 | 48-Macrocell EPLD |
| EP1810 | EPLD |
| EP1810EPLD | COMPLEX-EPLD 48-CELL 20NS PROP DELAY |