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EP2C50 Datasheet PDF

Altera EP2C50

The proliferation of I/O standards and the need for improved I/O performance have made it critical that low-cost devices have flexible I/O capabilities. With these aspects of implementation easily manipulated using the Altera® Quartus® II software, the Cyclone II device family enables system designers to use low cost FPGAs while keeping pace with increasing design complexity.
Part No. EP2C50
Datasheet EP2C50 Download
Manufacturer
Altera
Description ISDN Line Interface
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EP2C50 datasheet page 1 preview
Section IV. I/O Standards This section provides information on Cyclone™ II single-ended, voltage referenced, and differential I/O standards. This section includes the following chapters:
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● Chapter 10, Selectable I/O Standards in Cyclone II Devices Chapter 11, High-Speed Differential Interfaces in Cyclone II Devices Revision History The table below shows the revision history for Chapters 10 and 11. Chapter(s) 10 Date / Version Changes Made November 2004, Updated Table 10–7. v1.1 June 2004, v1.0 Added document to the Cyclone II Device Handbook. Updated Table 11–1. Updated Figures 11–4, 11–5, 11–7, and 11–8. 11 November 2004, v1.1
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● June 2004, v1.0 Added document to the Cyclone II Device Handbook. Altera Corporation Section IV–1 Preliminary 4U.com I/O Standards Cyclone II Device Handbook, Volume 1 Section IV–2 Preliminary Altera Corporation 4U.com Chapter 10. Selectable I/O Standards in Cyclone II Devices CII51010-1.1 Introduction Selectable I/O capabilities such as SSTL-18, SSTL-2, a...
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