EP2S180 Datasheet | Altera

Section I. Stratix II Device Family Data Sheet This section provides the data sheet specifications for Stratix® II devices. This section contains feature definitions of the internal architecture, configuration and JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, a reference to power consumption, and ordering information for Stratix II devices. This section contains the following chapters: - Chapter 1, Introduction - Chapter 2, Stratix II Architecture - Chapter 3, Configuration & Testing - Chapter 4, Hot Socketing & Power-On Reset - Chapter 5, DC & Switching Characteristics - Chapter 6, Reference & Ordering Information Revision History Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the full handbook. Altera Corporation Section I- 1 Stratix II Device Family Data Sheet Stratix II Device Handbook, Volume 1 Section I- 2 Altera Corporation 1. Introduction SII51001-4.2 Introduction Features Altera Corporation May 2007 The Stratix® II FPGA family is based on a 1.2-V, 90-nm, all-layer copper SRAM process and Features a new logic structure that maximizes performance, and enables device densities approaching 180,000 equivalent logic elements (LEs). Stratix II devices offer up to 9 Mbits of on-chip, Tri Matrix™ memory for demanding, memory intensive applications and has up to 96 DSP blocks with up to 384 (18-bit × 18-bit) multipliers for efficient implementation of high performance filters and other DSP functions. Various high-speed external memory interfaces are supported, including double data rate (DDR) SDRAM and DDR2 SDRAM, RLDRAM II, quad data rate (QDR) II SRAM, and single data rate (SDR) SDRAM. Stratix II devices support various I/O standards along with support for 1-gigabit per second (Gbps) source synchronous signaling with DPA circuitry. Stratix II devices offer a plete clock management...