Datasheet4U Logo Datasheet4U.com

EP2S30 - Stratix II Device

This page provides the datasheet information for the EP2S30, a member of the EP2S15 Stratix II Device family.

Features

  • Altera Corporation May 2007 The Stratix® II FPGA family is based on a 1.2-V, 90-nm, all-layer copper SRAM process and features a new logic structure that maximizes performance, and enables device densities approaching 180,000 equivalent logic elements (LEs). Stratix II devices offer up to 9 Mbits of on-chip, TriMatrix™ memory for demanding, memory intensive.

📥 Download Datasheet

Datasheet preview – EP2S30

Datasheet Details

Part number EP2S30
Manufacturer Altera
File Size 1.14 MB
Description Stratix II Device
Datasheet download datasheet EP2S30 Datasheet
Additional preview pages of the EP2S30 datasheet.
Other Datasheets by Altera

Full PDF Text Transcription

Click to expand full text
Section I. Stratix II Device Family Data Sheet This section provides the data sheet specifications for Stratix® II devices. This section contains feature definitions of the internal architecture, configuration and JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, a reference to power consumption, and ordering information for Stratix II devices. This section contains the following chapters: ■ Chapter 1, Introduction ■ Chapter 2, Stratix II Architecture ■ Chapter 3, Configuration & Testing ■ Chapter 4, Hot Socketing & Power-On Reset ■ Chapter 5, DC & Switching Characteristics ■ Chapter 6, Reference & Ordering Information Revision History Refer to each chapter for its own specific revision history.
Published: |