EP312 Description
The CMOS EPROM EP312 and EP324 devices have a versatile macrocell structure and I/O architecture, which allow them to implement highperformance logic functions effectively. The EP312 and EP324 input and macrocell.
EP312 Key Features
- binatorial speeds as fast as 25 ns
- Counter frequencies of up to 33.3 MHz
- 24-pin ceramic and plastic dual in-line package (CerDIP and PDIP)
- 28-pin plastic J-lead chip carrier (PLCC)
- 40-pin CerDIP and PDIP
- 44-pin PLCC One global Clock pin; one global Input Latch Enable/Input Clock/Input (ILE/ICLK/INPUT) pin Programmable “sta