Datasheet Details
| Part number | EP910I |
|---|---|
| Manufacturer | Altera |
| File Size | 657.80 KB |
| Description | EPLD |
| Datasheet |
 EP910I Datasheet
|
|
|
General Description
The Altera ClassicTM device family offers a solution to high-speed, lowpower logic integration.
Fabricated on advanced CMOS technology, Classic devices also have a Turbo-only version, which is described in this data sheet.
Key Features
- Classic ® EPLD Family Data Sheet s Complete device family with logic densities of 300 to 900 usable gates (see Table 1) s Device erasure and reprogramming with non-volatile EPROM configuration elements s Fast pin-to-pin logic delays as low as 10 ns and counter frequencies as high as 100 MHz s 24 to 68 pins available in dual in-line package (DIP), plastic J-lead chip carrier (PLCC), pin-grid array (PGA), and small-outline integrated circuit (SOIC) packages s Programmable security bit for protec.