EPF81188A Overview
11.1 ® FLEX 8000 Programmable Logic Device Family Data Sheet.
EPF81188A Key Features
- Low-cost, high-density, register-rich CMOS programmable logic device (PLD) family (see Table 1)
- 2,500 to 16,000 usable gates
- 282 to 1,500 registers
- System-level features
- In-circuit reconfigurability (ICR) via external configuration devices or intelligent controller
- Fully pliant with the peripheral ponent interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revis
- Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry pliant with IEEE Std. 1149.1-1990 on selected
- MultiVoltTM I/O interface enabling device core to run at 5.0 V, while I/O pins are patible with 5.0-V and 3.3-V logic le
- Low power consumption (typical specification is 0.5 mA or less in standby mode)
- Flexible interconnect