EPF81188A Datasheet PDF - Altera Programmable Logic Specs

EPF81188A - Programmable Logic

This page provides the datasheet information for the EPF81188A, a member of the FLEX8000 Programmable Logic family.

Datasheet Summary

Description

Altera’s Flexible Logic Element MatriX (FLEX®) family combines the benefits of both erasable programmable logic devices (EPLDs) and fieldprogrammable gate arrays (FPGAs).

Features

Low-cost, high-density, register-rich CMOS programmable logic device (PLD) family (see Table 1).
2,500 to 16,000 usable gates.
282 to 1,500 registers.
System-level features.
In-circuit reconfigurability (ICR) via external configuration devices or intelligent controller.
Fully compliant with the peripheral component interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 5.0-V operation.
Built-in Joint Te.

Datasheet Details

Part number	EPF81188A
Manufacturer	Altera
File Size	859.68 KB
Description	Programmable Logic
Datasheet	EPF81188A Datasheet
Additional preview pages of the EPF81188A datasheet.

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Full PDF Text Transcription

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January 2003, ver. 11.1 ® FLEX 8000 Programmable Logic Device Family Data Sheet 1 Features... ■ Low-cost, high-density, register-rich CMOS programmable logic device (PLD) family (see Table 1) – 2,500 to 16,000 usable gates – 282 to 1,500 registers ■ System-level features – In-circuit reconfigurability (ICR) via external configuration devices or intelligent controller – Fully compliant with the peripheral component interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 5.0-V operation – Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990 on selected devices – MultiVoltTM I/O interface enabling device core to run at 5.0 V, while I/O pins are compatible with 5.0-V and 3.

Published: Oct 31, 2019 |