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EPF81500A Datasheet PDF

Altera EPF81500A

The FLEX 8000 device family is ideal for a variety of applications because it combines the fine-grained architecture and high register count characteristics of FPGAs with the high speed and predictable interconnect delays of EPLDs. These devices are an excellent choice for bus interfaces, TTL integration, coprocessor functions, and high-speed controllers.
Part No. EPF81500A
Datasheet EPF81500A Download
Manufacturer
Altera
Description Programmable Logic
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EPF81500A datasheet page 1 preview

FEATURES

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● Low-cost, high-density, register-rich CMOS programmable logic device (PLD) family (see Table 1) – 2,500 to 16,000 usable gates – 282 to 1,500 registers
● System-level features – In-circuit reconfigurability (ICR) via external configuration devices or intelligent controller – Fully compliant with the peripheral component interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 5.0-V operation – Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990 on selected devices – MultiVoltTM I/O interface enabling device core to run at 5.0 V, while I/O pins are compatible with 5.0-V and 3.3-V logic levels – Low power consumption (typical specification is 0.5 mA or less in standby mode)
● Flexible interconnect – FastTrack® Interconnect continuous routing structure for fast, predictable interconnect delays – Dedicated carry chain that implements arithmetic functions such as fast adders, counter...
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