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EPM3064A - Programmable Logic

This page provides the datasheet information for the EPM3064A, a member of the EPM3032A Programmable Logic family.

Datasheet Summary

Description

PCI compatible Bus friendly architecture including programmable slew rate control Open drain output option Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls Programmable power saving mode fo

Features

  • High.
  • performance, low.
  • cost CMOS EEPROM.
  • based programmable logic devices (PLDs) built on a MAX® architecture (see Table 1).
  • 3.3-V in-system programmability (ISP) through the built.
  • in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability.
  • ISP circuitry compliant with IEEE Std. 1532.
  • Built.
  • in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990.
  • Enhanced ISP features:.

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Datasheet preview – EPM3064A

Datasheet Details

Part number EPM3064A
Manufacturer Altera
File Size 729.56 KB
Description Programmable Logic
Datasheet download datasheet EPM3064A Datasheet
Additional preview pages of the EPM3064A datasheet.

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Full PDF Text Transcription

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June 2006, ver. 3.5 ® MAX 3000A Programmable Logic Device Family Data Sheet Features... ■ High–performance, low–cost CMOS EEPROM–based programmable logic devices (PLDs) built on a MAX® architecture (see Table 1) ■ 3.3-V in-system programmability (ISP) through the built–in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability – ISP circuitry compliant with IEEE Std. 1532 ■ Built–in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990 ■ Enhanced ISP features: – Enhanced ISP algorithm for faster programming – ISP_Done bit to ensure complete programming – Pull-up resistor on I/O pins during in–system programming ■ High–density PLDs ranging from 600 to 10,000 usable gates ■ 4.
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