EPM5128 Datasheet | Altera

Features ... s Advanced Multiple Array Matri X (MAX) 5000 architecture bining speed and ease-of-use of PAL devices with the density of programmable gate arrays s plete family of high-performance, erasable CMOS EPROM EPLDs for designs ranging from fast 28-pin address decoders to 100-pin LSI custom peripherals s 600 to 3,750 usable gates (see Table 1) s Fast, 15-ns binatorial delays and 83.3-MHz counter frequencies s Configurable expander product-term distribution allowing more than 32 product terms in a single macrocell s 28 to 100 pins available in DIP, J-lead, PGA, SOIC, and QFP packages s Programmable registers providing D, T, JK, and SR flipflop functionality with individual clear, preset, and clock controls s Programmable security bit for protection of proprietary designs s Software design support featuring Altera’s MAX+PLUS II development system on 486- or Pentium-based PCs, and Sun SPARCstation, HP 9000 Series 700, and IBM RISC System/6000 workstations Table 1. MAX 5000 Device Features Feature Usable gates Macrocells Logic array blocks (LABs) Expanders Routing Maximum user I/O pins t PD (ns) t ASU (ns) t CO (ns) f CNT (MHz) EPM5032 600 32 1 64 Global 24 15 4 10 76.9 EPM5064 1,250 64 4 128 PIA 36 25 4 14 50 2,500 128 8 256 PIA 60 25 4 14 50 EPM5130 2,500 128 8 256 PIA 68, 84 25 4 14 50 EPM5192 3,750 192 12 384 PIA 72 25 4 14 50 Altera Corporation A-DS-M5000-03 MAX 5000 Programmable Logic Device Family Data Sheet ...and More Features General Description s Programming support with Altera’s Master Programming Unit (MPU) or programming hardware from other manufacturers s Additional design entry and simulation support provided by EDIF, LPM, Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Data I/O, Exemplar, Mentor Graphics, MINC, Or CAD, Synopsys, Veri Best, and Viewlogic The MAX 5000 family bines innovative architecture and advanced process technologies to offer optimum performance, flexibility, and...