EPM7064 Datasheet | Altera

eatures... f - High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX® architecture - 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices - ISP circuitry patible with IEEE Std. 1532 - Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices - Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells - plete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2) - 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect) - PCI-pliant devices available For information on in-system programmable 3.3-V MAX 7000A or 2.5-V MAX 7000B devices, see the MAX 7000A Programmable Logic Device Family Data Sheet or the MAX 7000B Programmable Logic Device Family Data Sheet. Table 1. MAX 7000 Device Features Feature EPM7032 Usable gates Macrocells Logic array blocks Maximum user I/O pins t PD (ns) t SU (ns) t FSU (ns) t CO1 (ns) f CNT (MHz) 32 2 6 5 2.5 4 151.5 1,250 64 4 6 5 2.5 4 151.5 EPM7096 EPM7128E EPM7160E EPM7192E EPM7256E 1,800 2,500 3,200 3,750 5,000 96 128 160 192 256 6 8 10 12 16 76 100 104 124 164 7.5 6 3 4.5...