PA7572 Datasheet PDF

Anachip PA7572

The PA7572 is a member of the Programmable Electrically Erasable Logic (PEEL™) Array family based on Anachip’s CMOS EEPROM technology. The PA7572 offers a versatile logic array architecture with 24 I/O pins, 14 input pins and 60 registers/latches (24 buried logic cells, 12 input registers/latches, 24 buried I/O registers/latches). Its logic array implements 100 sum-of-products logic functions divided into two groups each serving 12 logic cells.

Part No.	PA7572
Datasheet	PA7572 Download
Manufacturer	Anachip
Description	Programmable Electrically Erasable Logic
Buy	Stock & Price

APPLICATIONS

- Integration of multiple PLDs and random logic - Buried counters, complex state-machines - Comparators, decoders, other wide-gate functions CMOS Electrically Erasable Technology - Reprogrammable in 40-pin DIP, 44-pin PLCC and TQFP packages Flexible Logic Cell - Up to 3 output functions per logic cell - D,T and JK registers with special features - Independent or global clocks, resets, presets, clock polarity and output enables - Sum-of-products logic for output enables Development and Programmer Support - ICT PLACE Development Software - Fitters for ABEL, CUPL and other software - Programming support by popular third-party programmers

GENERAL DESCRIPTION

PEEL™ Arrays free designers from the limitations of ordinary PLDs by providing the architectural flexibility and speed needed for today’s programmable logic designs. Each group shares half (60) of the 120 product-terms available. The PA7572’s logic and I/O cells (LCCs, IOCs) are extremely flexible with up to three output functions per cell (a total of 72 for all 24 logic cells).