PA7572 Datasheet | Anachip

features - Independent or global clocks, resets, presets, clock polarity and output enables - Sum-of-products logic for output enables Development and Programmer Support - ICT PLACE Development Software - Fitters for ABEL, CUPL and other software - Programming support by popular third-party programmers General Description The PA7572 is a member of the Programmable Electrically Erasable Logic (PEEL™) Array family based on Anachip’s CMOS EEPROM technology. PEEL™ Arrays free designers from the limitations of ordinary PLDs by providing the architectural flexibility and speed needed for today’s programmable logic designs. The PA7572 offers a versatile logic array architecture with 24 I/O pins, 14 input pins and 60 registers/latches (24 buried logic cells, 12 input registers/latches, 24 buried I/O registers/latches). Its logic array implements 100 sum-of-products logic functions divided into two groups each serving 12 logic cells. Each group shares half (60) of the 120 product-terms available. The PA7572’s logic and I/O cells (LCCs, IOCs) are extremely flexible with up to three output functions per cell (a total of 72 for all 24 logic cells). Cells are configurable as D, T, and JK registers with independent or global clocks, resets, presets, clock polarity, and other features , making the PA7572 suitable for a variety of binatorial, synchronous and asynchronous logic applications. The PA7572 supports speeds as fast as 13ns/20ns (tpdi/tpdx) and 66.6MHz (f MAX) at moderate power consumption 140m A (100m A typical). Packaging includes 40-pin DIP and 44-pin PLCC (see Figure 1). Anachip and popular third-party development tool manufacturers provide development and programming support for the PA7572. Figure 1. Pin Configuration DIP (600 mil) I/CLK1 I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I G ND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O...