FEATURES
PLL generated or direct master clock Low EMI design DAC with 110 dB dynamic range and SNR −96 dB THD + N 3.3 V single supply Tolerance for 5 V logic inputs Supports 24 bits and 8 kHz to 192 kHz sample rates Differential DAC output Log volume control with autoramp function SPI® controllable for flexibility Software-controllable clickless mute Software power-down Right-justified, left-justified, I2S, and TDM modes Master and slave modes up to 16-channel input/output 64-lead LQFP GENERAL DESCRIPTION
patented multibit sigmadelta (Σ-Δ) architecture. An SPI port is included, allowing a microcontroller to adjust volume and many other parameters. Other members of this family include a single-ended DAC output and I2C® control port version. The AD1933 is designed for low EMI. This consideration is apparent in both the system and circuit design architectures. By using the on-board PLL to derive the master clock from the LR clock or from an external crystal, the AD1933 eliminates the need for a separate high frequency master clock and can also be used with a suppressed bit clock.
Analog Devices
