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AD4114 - 24-Bit Sigma-Delta ADC

General Description

The AD4114 is a low power, low noise, 24-bit, sigma-delta (Σ-Δ) analog-to-digital converter (ADC) that integrates an analog front end (AFE) for eight fully differential or 16 single-ended, high impedance (≥1 MΩ), bipolar, ±10 V voltage inputs.

Key Features

  • 24-bit ADC with integrated AFE Fast and flexible output rate: 1.25 SPS to 31.25 kSPS Channel scan data rate of 6.21 kSPS per channel (161 µs settling) 17.3 noise free bits at 1007 SPS per channel 120 dB common mode rejection of 50 Hz and 60 Hz at 20 SPS per channel ±10 V inputs, either 8 differential or 16 single-ended VIN pin absolute maximum rating: ±65 V Absolute input pin voltage up to ±20 V Minimum 1 MΩ impedance 0.07% TUE at 25°C On-chip 2.5 V reference ±0.12% initial accuracy at 25°C, ±5.

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Other Datasheets by Analog Devices

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AD4110-1 Universal Input Analog Front End
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Single Supply, Multichannel, 31.25 kSPS, 24-Bit, Sigma-Delta ADC with ±10 V Inputs Data Sheet AD4114 FEATURES 24-bit ADC with integrated AFE Fast and flexible output rate: 1.25 SPS to 31.25 kSPS Channel scan data rate of 6.21 kSPS per channel (161 µs settling) 17.3 noise free bits at 1007 SPS per channel 120 dB common mode rejection of 50 Hz and 60 Hz at 20 SPS per channel ±10 V inputs, either 8 differential or 16 single-ended VIN pin absolute maximum rating: ±65 V Absolute input pin voltage up to ±20 V Minimum 1 MΩ impedance 0.07% TUE at 25°C On-chip 2.5 V reference ±0.12% initial accuracy at 25°C, ±5 ppm/°C (typical) drift Internal or external clock Power supplies AVDD = 3.0 V to 5.5 V IOVDD = 2 V to 5.5 V Total current consumption AVDD + IOVDD (IDD) = 3.