AD5335 Datasheet | Analog Devices

a 2.5 V to 5.5 V, 500 ␮A, Parallel Interface Quad Voltage-Output 8-/10-/12-Bit DACs AD5334/AD5335/AD5336/AD5344- Features AD5334: Quad 8-Bit DAC in 24-Lead TSSOP AD5335: Quad 10-Bit DAC in 24-Lead TSSOP AD5336: Quad 10-Bit DAC in 28-Lead TSSOP AD5344: Quad 12-Bit DAC in 28-Lead TSSOP Low Power Operation: 500 ␮A @ 3 V, 600 ␮A @ 5 V Power-Down to 80 n A @ 3 V, 200 n A @ 5 V via PD Pin 2.5 V to 5.5 V Power Supply Double-Buffered Input Logic Guaranteed Monotonic by Design Over All Codes Output Range: 0- VREF or 0- 2 VREF Power-On Reset to Zero Volts Simultaneous Update of DAC Outputs via LDAC Pin Asynchronous CLR Facility Low Power Parallel Data Interface On-Chip Rail-to-Rail Output Buffer Amplifiers Temperature Range: - 40؇C to +105؇C APPLICATIONS Portable Battery-Powered Instruments Digital Gain and Offset Adjustment Programmable Voltage and Current Sources Programmable Attenuators Industrial Process Control GENERAL DESCRIPTION The AD5334/AD5335/AD5336/AD5344 are quad 8-, 10-, and 12-bit DACs. They operate from a 2.5 V to 5.5 V supply consuming just 500 µA at 3 V, and feature a power-down mode that further reduces the current to 80 n A. These devices incorporate an on-chip output buffer that can drive the output to both supply rails. The AD5334/AD5335/AD5336/AD5344 have a parallel interface. CS selects the device and data is loaded into the input registers on the rising edge of WR. The GAIN pin on the AD5334 and AD5336 allows the output range to be set at 0 V to VREF or 0 V to 2 × VREF. Input data to the DACs is double-buffered, allowing simultaneous update of multiple DACs in a system using the LDAC pin. On the AD5334, AD5335 and AD5336 an asynchronous CLR input is also provided. This resets the contents of the Input Register and the DAC Register to all zeros. These devices also incorporate a power-on-reset circuit that ensures that the DAC output powers on to 0 V and remains there until valid data is written to the device. The AD5334/AD5335/AD5336/AD5344 are available...