AD5689R Datasheet | Analog Devices

Data Sheet Dual, 16-/12-Bit nano DAC+ with 2 ppm/°C Reference, SPI Interface AD5689R/AD5687R INTERFACE LOGIC 11256-001 Features High relative accuracy (INL): ±2 LSB maximum at 16 bits Low drift 2.5 V reference: 2 ppm/°C typical Tiny package: 3 mm × 3 mm, 16-lead LFCSP TUE: ±0.1% of FSR maximum Offset error: ±1.5 m V maximum Gain error: ±0.1% of FSR maximum High drive capability: 20 m A, 0.5 V from supply rails User-selectable gain of 1 or 2 (GAIN pin) Reset to zero scale or midscale (RSTSEL pin) 1.8 V logic patibility 50 MHz SPI with readback or daisy chain Low glitch: 0.5 n V-sec Low power: 3.3 m W at 3 V 2.7 V to 5.5 V power supply - 40°C to +105°C temperature range AEC-Q100 qualified for automotive applications APPLICATIONS Optical transceivers Base station power amplifiers Process control (PLC I/O cards) Industrial automation Data acquisition systems GENERAL DESCRIPTION The AD5689R/AD5687R members of the nano DAC+™ family are low power, dual, 16-/12-bit buffered voltage output digital-to-analog converters (DACs). The devices include a 2.5 V, 2 ppm/°C internal reference (enabled by default) and a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The devices operate from a single 2.7 V to 5.5 V supply, are guaranteed monotonic by design, and exhibit less than 0.1% FSR gain error and 1.5 m V offset error performance. Both devices are available in a 3 mm × 3 mm LFCSP and a TSSOP package. The AD5689R/AD5687R also incorporate a power-on reset circuit and a RSTSEL pin that ensure that the DAC outputs power up to zero scale or midscale and remain there until a valid write takes place. Each part contains a per channel power-down feature that reduces the current consumption of the device to 4 μA at 3 V while in power-down mode. The AD5689R/AD5687R use a versatile serial peripheral interface (SPI) that operates at clock rates up to 50 MHz. Both devices contain a VLOGIC pin that is intended for 1.8 V/3 V/5 V logic. VLOGIC SCLK SYNC...