Datasheet4U Logo Datasheet4U.com

AD6649 - IF Diversity Receiver

Description

The AD6649 is a mixed-signal intermediate frequency (IF) receiver consisting of dual 14-bit, 250 MSPS ADCs and a wideband digital downconverter (DDC).

Features

  • SNR = 73.0 dBFS in a 95 MHz bandwidth at 185 MHz AIN and 245.76 MSPS.
  • SFDR = 85 dBc at 185 MHz AIN and 250 MSPS.
  • Noise density =.
  • 151.2 dBFS/Hz input at 185 MHz,.
  • 1 dBFS AIN and 250 MSPS.
  • Total power consumption: 1 W with fixed-frequency NCO, 95 MHz FIR filter.
  • 1.8 V supply voltages.
  • LVDS (ANSI-644 levels) outputs.
  • Integer 1-to-8 input clock divider (625 MHz maximum input).
  • Integrated dual-channel ADC.
  • Sample rates of up to 250 MSPS.

📥 Download Datasheet

📁 Similar Datasheet

  • AD6025GP - Fan (ADDA)
  • AD60D60 - 60V 60A Ultra Low VF Schottky (AP Semiconductor)
  • AD620ARZ-REEL - Low Cost Precision Instrument Amplifier (tokmas)
  • AD62384AF - 8CH LOW INPUT ACTIVE DARLINGTON SINK DRIVER (Toshiba Semiconductor)
  • AD62384AP - 8CH LOW INPUT ACTIVE DARLINGTON SINK DRIVER (Toshiba Semiconductor)
  • AD62384F - 8CH LOW INPUT ACTIVE DARLINGTON SINK DRIVER (Toshiba Semiconductor)
  • AD62385AF - 8CH LOW INPUT ACTIVE DARLINGTON SINK DRIVER (Toshiba Semiconductor)
  • AD62385AP - 8CH LOW INPUT ACTIVE DARLINGTON SINK DRIVER (Toshiba Semiconductor)
  • AD62385F - 8CH LOW INPUT ACTIVE DARLINGTON SINK DRIVER (Toshiba Semiconductor)
  • AD62386AF - 8CH LOW INPUT ACTIVE DARLINGTON SINK DRIVER (Toshiba Semiconductor)
Other Datasheets by Analog Devices
  • AD664 - Monolithic 12-Bit Quad DAC
  • AD6640 - 12-Bit/ 65 MSPS IF Sampling A/D Converter
  • AD6641 - 250 MHz Bandwidth DPD Observation Receiver
  • AD6642 - Dual IF Receiver
  • AD6643 - Dual IF Receiver
  • AD6644 - 40 MSPS/65 MSPS Analog-to-Digital Converter
  • AD6645 - 80MSPS / 105MSPS A/D Converter
  • AD660 - Monolithic 16-Bit Serial/Byte DACPORT

Full PDF Text Transcription

Click to expand full text
Data Sheet AD6649 IF Diversity Receiver FEATURES ► SNR = 73.0 dBFS in a 95 MHz bandwidth at 185 MHz AIN and 245.76 MSPS ► SFDR = 85 dBc at 185 MHz AIN and 250 MSPS ► Noise density = −151.2 dBFS/Hz input at 185 MHz, −1 dBFS AIN and 250 MSPS ► Total power consumption: 1 W with fixed-frequency NCO, 95 MHz FIR filter ► 1.8 V supply voltages ► LVDS (ANSI-644 levels) outputs ► Integer 1-to-8 input clock divider (625 MHz maximum input) ► Integrated dual-channel ADC ► Sample rates of up to 250 MSPS ► IF sampling frequencies to 400 MHz ► Internal ADC voltage reference ► Flexible input range (1.4 V p-p to 2.1 V p-p (1.
Published: |