FEATURES
► SNR = 73.0 dBFS in a 95 MHz bandwidth at 185 MHz AIN and 245.76 MSPS ► SFDR = 85 dBc at 185 MHz AIN and 250 MSPS ► Noise density = −151.2 dBFS/Hz input at 185 MHz, −1 dBFS AIN and 250 MSPS ► Total power consumption: 1 W with fixed-frequency NCO, 95 MHz FIR filter ► 1.8 V supply voltages ► LVDS (ANSI-644 levels) outputs ► Integer 1-to-8 input clock divider (625 MHz maximum input) ► Integrated dual-channel ADC ► Sample rates of up to 250 MSPS ► IF sampling frequencies to 400 MHz ► Internal ADC voltage reference ► Flexible input range (1.4 V p-p to 2.1 V p-p (1.75 V p-p nominal)) ► ADC clock duty cycle stabilizer ► 95 dB channel isolation/crosstalk ► Integrated wideband digital processor ► 32-bit complex numerically controlled oscillator (NCO) ► FIR filter with 2 modes ► Real output from an fS/4 output NCO ► Amplitude detect bits for efficient AGC implementation ► Energy saving power-down modes ► Decimated, interleaved real LVDS data outputs APPLICATIONS
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Analog Devices
