AD73422 Datasheet | Analog Devices

FEATURES AFE PERFORMANCE Two 16-Bit A/D Converters Two 16-Bit D/A Converters Programmable Input/Output Sample Rates 78 d B ADC SNR 77 d B DAC SNR 64 k S/s Maximum Sample Rate - 90 d B Crosstalk Low Group Delay (25 ␮s Typ per ADC Channel, 50 ␮s Typ per DAC Channel) Programmable Input/Output Gain On-Chip Reference DSP PERFORMANCE 19 ns Instruction Cycle Time @ 3.3 V, 52 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions Power-Down Mode Featuring Low CMOS Standby Power Dissipation with 400 Cycle Recovery from Power-Down Condition Low Power Dissipation in Idle Mode GENERAL DESCRIPTION FULL MEMORY MODE PROGRAMMABLE I/O AND FLAGS EXTERNAL ADDRESS BUS EXTERNAL DATA BUS BYTE DMA CONTROLLER OR EXTERNAL DATA BUS TIMER INTERNAL DMA PORT HOST MODE PROGRAM SEQUENCER PROGRAM MEMORY ADDRESS DATA MEMORY ADDRESS PROGRAM MEMORY DATA DATA MEMORY DATA ARITHMETIC UNITS ALU MAC SHIFTER ADSP-2100 BASE ARCHITECTURE SERIAL PORTS SPORT 0 SPORT 1 SERIAL PORT SPORT 2 ADC1 DAC1 ADC2 DAC2 ANALOG FRONT END SECTION applications. The A/D and D/A conversion channels feature programmable input/output gains with ranges 38 d B and 21 d B respectively. An on-chip reference voltage is included to allow single supply operation. The sampling rate of the AFE is programmable with four separate settings offering 64, 32, 16 and 8 k Hz sampling rates (from a master clock of 16.384 MHz), while the serial port (SPORT2) allows easy expansion of the number of I/O channels by cascading extra AFEs external to the AD73422. The AD73422’s DSP engine bines the ADSP-2100 family base architecture (three putational units, data address generators and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities and on-chip program and data memory. The AD73422-80 integrates 80K bytes of...