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AD7612 - 16-bit charge redistribution successive approximation register

Description

The AD7612 is a 16-bit charge redistribution successive approximation register (SAR), architecture analog-to-digital converter (ADC) fabricated on Analog Devices, Inc.’s iCMOS high voltage process.

Features

  • Multiple pins/software programmable input ranges: 5 V, 10 V, ±5 V, ±10 V Pins or serial SPI®-compatible input ranges/mode selection Throughput 750 kSPS (warp mode) 600 kSPS (normal mode) 500 kSPS (impulse mode) INL: ±0.75 LSB typical, ±1.5 LSB maximum (±23 ppm of FSR) 16-bit resolution with no missing codes SNR: 92 minimum (5 V) @ 2 kHz, 94 dB typical (±10 V) @ 2 kHz THD:.
  • 107 dB typical iCMOS™ process technology 5 V internal reference: typical drift 3 ppm/°C; TEMP output No pipeline del.

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Datasheet preview – AD7612

Datasheet Details

Part number AD7612
Manufacturer Analog Devices
File Size 518.86 KB
Description 16-bit charge redistribution successive approximation register
Datasheet download datasheet AD7612 Datasheet
Additional preview pages of the AD7612 datasheet.

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Full PDF Text Transcription

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16-Bit, 750 kSPS, Unipolar/Bipolar Programmable Input PulSAR® ADC AD7612 FEATURES Multiple pins/software programmable input ranges: 5 V, 10 V, ±5 V, ±10 V Pins or serial SPI®-compatible input ranges/mode selection Throughput 750 kSPS (warp mode) 600 kSPS (normal mode) 500 kSPS (impulse mode) INL: ±0.75 LSB typical, ±1.5 LSB maximum (±23 ppm of FSR) 16-bit resolution with no missing codes SNR: 92 minimum (5 V) @ 2 kHz, 94 dB typical (±10 V) @ 2 kHz THD: −107 dB typical iCMOS™ process technology 5 V internal reference: typical drift 3 ppm/°C; TEMP output No pipeline delay (SAR architecture) Parallel (16- or 8-bit bus) and serial 5 V/3.
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