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AD7626 - PulSAR Differential ADC

Description

The AD7626 is a 16-bit, 10 MSPS, charge redistribution successive approximation register (SAR) based architecture analog-to-digital converter (ADC).

SAR architecture allows unmatched performance both in noise (91.5 dB SNR) and in linearity (±0.45 LSB INL).

Features

  • Throughput: 10 MSPS SNR: 91.5 dB 16-bit no missing codes INL: ±0.45 LSB DNL: ±0.35 LSB Power dissipation: 136mW 32-lead LFCSP (5 mm × 5 mm) SAR architecture No latency/no pipeline delay 16-bit resolution with no missing codes Zero error: ±1LSB Differential input range: ±4.096 V Serial LVDS interface Self-clocked mode Echoed-clock mode LVDS or CMOS option for conversion control (CNV signal) Reference options Internal: 4.096 V External (1.2 V) buffered to 4.096 V External: 4.096 V.

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Datasheet preview – AD7626

Datasheet Details

Part number AD7626
Manufacturer Analog Devices
File Size 963.21 KB
Description PulSAR Differential ADC
Datasheet download datasheet AD7626 Datasheet
Additional preview pages of the AD7626 datasheet.

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Full PDF Text Transcription

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16-Bit, 10 MSPS, PulSAR Differential ADC AD7626 FEATURES Throughput: 10 MSPS SNR: 91.5 dB 16-bit no missing codes INL: ±0.45 LSB DNL: ±0.35 LSB Power dissipation: 136mW 32-lead LFCSP (5 mm × 5 mm) SAR architecture No latency/no pipeline delay 16-bit resolution with no missing codes Zero error: ±1LSB Differential input range: ±4.096 V Serial LVDS interface Self-clocked mode Echoed-clock mode LVDS or CMOS option for conversion control (CNV signal) Reference options Internal: 4.096 V External (1.2 V) buffered to 4.096 V External: 4.096 V FUNCTIONAL BLOCK DIAGRAM REFIN REF VCM 1.2V BAND GAP IN+ IN– CAP DAC VIO LOGIC CNV+, CNV– D+, D– CLK+, CLK– 07648-001 ÷2 CLOCK AD7626 SAR SERIAL LVDS DCO+, DCO– Figure 1.
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