AD7937 Datasheet | Analog Devices

FEATURES Two 12-Bit DACs in One Package DAC Ladder Resistance Matching: 0.5% Surface-Mount Package 4-Quadrant Multiplication Low Gain Error (3 LSB max Over Temperature) Byte Loading Structure Fast Interface Timing APPLICATIONS Automatic Test Equipment Programmable Filters Audio Applications Synchro Applications Process Control LC2MOS (8+4) Loading Dual 12-Bit DAC AD7937 FUNCTIONAL BLOCK DIAGRAM DAC A MS INPUT REG 4 DAC A LS INPUT REG 8 DAC A REGISTER UPD 12 DAC A A1 IOUTA AGNDA RFBA A0 CONTROL LOGIC CS WR VREFA VREFB RFBB GENERAL DESCRIPTION DAC B 12 DAC B REGISTER 4 DAC B MS INPUT REG 8 DAC B LS INPUT REG IOUTB AGNDB The AD7937 contains two 12-bit current output DACs on one monolithic chip. A separate reference input is provided for each DAC. The dual DAC saves valuable board space, and the monolithic construction ensures excellent thermal tracking. Both DACs are guaranteed 12-bit monotonic over the full temperature range. The AD7937 has a 2-byte (eight LSBs, four MSBs) loading structure. It is designed for right-justified data format. The control signals for register loading are A0, A1, CS, WR, and UPD. Data is loaded to the input registers when CS and WR are low. To transfer this data to the DAC registers, UPD must be taken low with WR. Added features on the AD7937 include an asynchronous CLR line which is very useful in calibration routines. When this is taken low, all registers are cleared. The double buffering of the data inputs allows simultaneous update of both DACs. Also, each DAC has a separate AGND line. This increases the device versatility; for instance, one DAC may be operated with AGND biased while the other is connected in the standard configuration. The AD7937 is manufactured using the Linear patible CMOS (LC2MOS) process. It is speed patible with most microprocessors and accepts TTL, 74HC, and 5 V CMOS logic level inputs. DB7- DB0 DGND PRODUCT HIGHLIGHTS 1. DAC-to-DAC Matching Since both DACs are fabricated on the same...